coreboot on the MSI MS-6117 (Intel 440LX)

This project documents the ongoing effort to port coreboot to motherboards based on the Intel 440LX chipset, with a specific focus on the MSI MS‑6117 (LX6). The 440LX was a cornerstone of the Slot 1 era, powering countless Pentium II systems. Bringing modern open‑source firmware to this hardware helps preserve it and break free from its proprietary BIOS limitations.

MSI MS-6117 Motherboard

The target: an MSI MS‑6117 LX6 Slot 1 motherboard based on the Intel 440LX chipset.

Reference Links

Mainboard details and documentation on the MSI MS‑6117 (LX6) at Theretroweb: MSI MS‑6117 LX6
Intel 440LX chipset reference design and datasheets on Theretroweb: Intel 440LX Customer Reference Design

Key Features & Status

Chipset Support: Native northbridge driver for Intel 82443LX “PAC” Host‑to‑PCI Bridge
Memory Initialization: raminit supports both SDRAM and EDO DRAM
Board Quirk Workaround: Handles MS‑6117 reversed DIMM slot mapping
Payload Support: Boots to a SeaBIOS payload
AGP Limit: AGP is currently disabled due to initialization lock‑ups—board only works in PCI‑only mode
Open Source: Intended for upstream contribution to coreboot

Why coreboot on a 440LX?

Speed – Much faster boots than legacy BIOS
Control – Full visibility into hardware init
Flexibility – Run modern payloads like SeaBIOS, coreboot drivers, etc.
Preservation – Document and revive classic hardware for future enthusiasts

Technical Deep Dive

Memory Initialization (`raminit`)

The process includes:

200 µs power stability wait
NOP command
Precharge banks
CBR refresh cycles
Mode Register Set configuration
Enable normal operation

DIMMs are auto‑detected via SPD EEPROMs over SMBus.

MSI MS‑6117 Quirk: Reversed DIMM Slots

Standard 3‑DIMM mapping vs. MS‑6117 mapping:

DIMM Slot	Standard Addr	MS‑6117 Addr
DIMM 0	`0x50`	`0x52`
DIMM 1	`0x51`	`0x51`
DIMM 2	`0x52`	`0x50`

Handled via Kconfig option:

config SDRAM_3DIMM_REVERSE_OFFSET
  bool
  depends on NORTHBRIDGE_INTEL_I440LX
  default n
  help
    For MSI boards (e.g., MS‑6117, ATC‑6130) with reversed SPD address mapping,
    enable this option to reverse the read loop.

Known Limitations

AGP Initialization: Enabling AGP causes resource setup freeze. Only PCI‑only mode is currently stable.
Basic ACPI Support: ACPI tables are not yet fully implemented.

Current Status

✅ Booting reliably on MSI MS‑6117
✅ Stable SDRAM initialization
✅ DIMM SPD workaround implemented
✅ Linux and DOS payloads launching
⚠️ AGP disabled for now

Next Steps

Fix AGP bridge initialization
Implement full ACPI table support
Test on other 440LX boards (e.g. ATC‑6130)
Clean up code for coreboot Gerrit submission
Upstream the port into mainline coreboot

🔗 Additional Resources

— Rigo (0xcats)